Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

The dataset belongs to the IEEE TC paper "Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device". The research is about a novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA.