Evaluation and reduction of power dissipation in multicore systems based on Networks-on-Chip

Multicore chips are currently the norm in enterprise, scientific and desktop computing and have already made inroads into mobile and embedded computing. One of the major problems faced by multicore system designers is to achieve maximum performance and functionality while respecting the power dissipation budget, which limits how much energy the system can take from mains or batteries. The power budget should be set as low as possible, because of energy costs, impact on the environment, battery lifetime, cooling costs, among other factors. This project aims to investigate and develop design techniques to optimise multicores in such a way that they can perform the same functionality with the same level of performance, while dissipating less power. The main focus of the techniques addressed by this project is the on-chip communication infrastructure, which was introduced to allow the multiple processing cores to exchange data and can account for up to 30% of the total power dissipated by the chip. To maximise the impact of this research to the UK and European economy, the project will address system-level techniques which are available to local system design and integration companies, rather than technology-specific techniques that require control of the chip fabrication process, which is often outsourced.