The LowPowNoC project consisted of three work packages. The first
(WP1) involved the development of power consumption models for NoC interconnection architectures. These simulations were built on top of the group's existing lsi.noc simulation framework using the Ptolemy II simulator, and provided a high-speed evaluation methodology for the rest of the project components. Two new transaction-level models (TLM) were also added for fast simulation of non-preemptive NoCs, and power consumption modelling was added to our existing NoC simulation models. The power consumption tracking focused on link dynamic power consumption occurring during bit transitions on NoC link wires.
The second and third work packages explored task mapping, with WP2 exploring dynamic task remapping during system execution, and WP3 the integration of task mapping with network coding. For WP2, a remapping algorithm was produced which took into account the hop count, link congestion and relative packet sizes in making its remapping decisions, remapping the most needy flows to the closest available processing cores. WP3 focused on the integration of end-to-end coding with dynamic task mapping, and achieving power savings through the selection of distinct codes for individual flows.
Multicore chips are currently the norm in enterprise, scientific and desktop computing and have already made inroads into mobile and embedded computing. One of the major problems faced by multicore system designers is to achieve maximum performance and functionality while respecting the power dissipation budget, which limits how much energy the system can take from mains or batteries. The power budget should be set as low as possible, because of energy costs, impact on the environment, battery lifetime, cooling costs, among other factors. This project aims to investigate and develop design techniques to optimise multicores in such a way that they can perform the same functionality with the same level of performance, while dissipating less power. The main focus of the techniques addressed by this project is the on-chip communication infrastructure, which was introduced to allow the multiple processing cores to exchange data and can account for up to 30% of the total power dissipated by the chip. To maximise the impact of this research to the UK and European economy, the project will address system-level techniques which are available to local system design and integration companies, rather than technology-specific techniques that require control of the chip fabrication process, which is often outsourced.
The first workpackage of the project demonstrated that the new and modified transaction-level simulation models can retain high accuracy while being very fast, with a speed improvement of two to three orders of magnitude compared to cycle-accurate simulations. For the majority of packets in real and synthetic application case studies simulated, the latency simulation produced results accurate to within several flits. Results also showed that the aggregate power consumption from the TLM models is also accurate to within 2-3% of the values obtained from the cycle-accurate simulations.
The second work package showed that non-preemptive NoCs with dynamic task remapping can reduce power consumption and latency 30-40% compared to a static initial mapping in a priority preemptive NoC. This result was obtained in simulation with a real application case study. The third work package showed that coding-aware task mappers can reduce overall power consumption in NoCs compared to the conventional approach of separate mapping and coding, with a 15% power reduction demonstrated in simulation with synthetic traffic patterns.
|Effective start/end date
|26/03/12 → 25/12/13