Research output per year
Research output per year
Project Details
Description
A prototype processor array architecture , comprising of individual processor tiles, capable of connecting via magnetic connectors in 3 dimensions, provides the ability to rapidly assemble complex processor array topologies, and to evaluate power grid behaviours in such systems. An extension to this project provides the ability for arm-based processors to be integrated with tiles to form programmable processor grids.
Layman's description
This project focusses upon the development of a design concept for scalable processor arrays, from concept to a working hardware prototype demonstrator. The end result demonstrates the feasibility of tile-able computing modules which can be connected in three dimensional structures without the need for traditional circuit board and cabinet structures of the type usually found in large scale computing facilities.
Key findings
The system was built and successfully tested. This work supports the validation of related PhD research work focussed upon simulation of the same platforms.
| Short title | Hex-Tile Prototype Demonstrator |
|---|---|
| Status | Finished |
| Effective start/end date | 1/04/21 → 31/07/22 |
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Hex-Tile: Evaluation Prototype of a Novel Tile-based Processor Array: Preliminary Report
Crispin-Bailey, C., Austin, J., Thuphairo, P. & Moulds, A., 18 Aug 2022, 6 p.Research output: Other contribution
Open AccessFile -
Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility.
Crispin-Bailey, C., Austin, J., Moulds, A. & Thuphairo, P., 16 Jul 2022, Euromicro DSD 2022 Conference proceedings (TBC). IEEE, 8 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Open AccessFile