3D integrated circuit layout visualization using VRML

L S Indrusiak, R A D Reis

Research output: Contribution to journalArticlepeer-review

Abstract

This paper introduces the virtual reality modeling language (VRML) as a way to describe the layout of integrated circuits. Using this language, the circuit can be viewed in three dimensions, adding the depth dimension, not present in the regular layout description languages. A conversion tool that parses 2D circuit layout descriptions and converts it into 3D VRML models is presented. A discussion about other applications of VRML on integrated circuits design and on educational tools is also included. 

Original languageEnglish
Pages (from-to)503-511
Number of pages9
JournalFuture generation computer systems
Volume17
Issue number5
Publication statusPublished - Mar 2001

Keywords

  • integrated circuits
  • virtual reality
  • World Wide Web

Cite this