A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.

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A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the `simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um2. Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.
Original languageEnglish
Pages (from-to)1087-1100
Number of pages14
JournalIEEE Transactions on Biomedical Circuits and Systems
Issue number5
Early online date30 Aug 2019
Publication statusPublished - Oct 2019

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  • Lossless Data Compression
  • VLSI Design
  • EEG
  • ECG
  • Wearable Sensors
  • Power Efficiency

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