By the same authors

From the same journal

A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.

Research output: Contribution to journal › Article › peer-review

Standard

A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. / Crispin-Bailey, Christopher; Dai, Chengliang; Austin, James.

In: IEEE Transactions on Biomedical Circuits and Systems, Vol. 13, No. 5, 10.2019, p. 1087-1100.

Research output: Contribution to journal › Article › peer-review

Harvard

Crispin-Bailey, C, Dai, C & Austin, J 2019, 'A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.', IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 5, pp. 1087-1100. https://doi.org/10.1109/TBCAS.2019.2938672

APA

Crispin-Bailey, C., Dai, C., & Austin, J. (2019). A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. IEEE Transactions on Biomedical Circuits and Systems, 13(5), 1087-1100. https://doi.org/10.1109/TBCAS.2019.2938672

Vancouver

Crispin-Bailey C, Dai C, Austin J. A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. IEEE Transactions on Biomedical Circuits and Systems. 2019 Oct;13(5):1087-1100. https://doi.org/10.1109/TBCAS.2019.2938672

Author

Crispin-Bailey, Christopher ; Dai, Chengliang ; Austin, James. / A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit. In: IEEE Transactions on Biomedical Circuits and Systems. 2019 ; Vol. 13, No. 5. pp. 1087-1100.

Bibtex - Download

@article{5772a5d5624247d5ab3e55ced42c27a0,
title = "A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.",
abstract = "A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the `simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um2. Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.",
keywords = "Lossless Data Compression, VLSI Design, EEG, ECG, Wearable Sensors, Power Efficiency",
author = "Christopher Crispin-Bailey and Chengliang Dai and James Austin",
note = "(c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.",
year = "2019",
month = oct,
doi = "10.1109/TBCAS.2019.2938672",
language = "English",
volume = "13",
pages = "1087--1100",
journal = "IEEE Transactions on Biomedical Circuits and Systems",
issn = "1932-4545",
publisher = "IEEE",
number = "5",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - A 65nm CMOS lossless bio-signal compression circuit with 250 femtoJoule performance per bit.

AU - Crispin-Bailey, Christopher

AU - Dai, Chengliang

AU - Austin, James

N1 - (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

PY - 2019/10

Y1 - 2019/10

N2 - A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the `simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um2. Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.

AB - A 65nm CMOS integrated circuit implementation of a bio-physiological signal compression device is presented, reporting exceptionally low power, and extremely low silicon area cost, relative to state-of-the-art. A novel `xor-log2-sub-band' data compression scheme is evaluated, achieving modest compression, but with very low resource cost. With the intent to design the `simplest useful compression algorithm', the outcome is demonstrated to be very favourable where power must be saved by trading off compression effort against data storage capacity, or data transmission power, even where more complex algorithms can deliver higher compression ratios. A VLSI design and fabricated Integrated Circuit implementation are presented, and estimated performance gains and efficiency measures for various bio-medical use-cases are given. Power costs as low as 1.2 pJ per sample-bit are suggested for a 10kSa/s data-rate, whilst utilizing a power-gating scenario, and dropping to 250fJ/bit at continuous conversion data-rates of 5MSa/sec. This is achieved with a diminutive circuit area of 155 um2. Both power and area appear to be state-of-the-art in terms of compression versus resource cost, and this yields benefit for system optimization.

KW - Lossless Data Compression

KW - VLSI Design

KW - EEG

KW - ECG

KW - Wearable Sensors

KW - Power Efficiency

U2 - 10.1109/TBCAS.2019.2938672

DO - 10.1109/TBCAS.2019.2938672

M3 - Article

VL - 13

SP - 1087

EP - 1100

JO - IEEE Transactions on Biomedical Circuits and Systems

JF - IEEE Transactions on Biomedical Circuits and Systems

SN - 1932-4545

IS - 5

ER -

York staff: edit these data