A 65nm SILICON CHIP IMPLEMENTATION of a Novel Data Compression Circuit and Algorithm

TY - ADVS

T1 - A 65nm SILICON CHIP IMPLEMENTATION of a Novel Data Compression Circuit and Algorithm

AU - Crispin-Bailey, Christopher

AU - Dai, Chengliang

PY - 2015/4

Y1 - 2015/4

N2 - The Log2 Compression Technique, Developed at York by Bailey and Dai (2014) is implemented in 65nm CMOS as a fully functional silicon chip prototype, manufactured by UMC semiconductors through the Europractice Foundry Access Programme.

AB - The Log2 Compression Technique, Developed at York by Bailey and Dai (2014) is implemented in 65nm CMOS as a fully functional silicon chip prototype, manufactured by UMC semiconductors through the Europractice Foundry Access Programme.

M3 - Artefact

ER -