A 65nm SILICON CHIP IMPLEMENTATION of a Novel Data Compression Circuit and Algorithm

Research output: Non-textual formArtefact


The Log2 Compression Technique, Developed at York by Bailey and Dai (2014) is implemented in 65nm CMOS as a fully functional silicon chip prototype, manufactured by UMC semiconductors through the Europractice Foundry Access Programme.
Original languageEnglish
Publication statusPublished - Apr 2015

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