A Generic and Compositional Framework for Multicore Response Time Analysis

Sebastian Altmeyer, Robert Ian Davis, Leandro Soares Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework. This framework is extensible to different multicore architectures, with various types and arrangements of
local memory, and different arbitration policies for the common
interconnects. We instantiate the framework for single level local
data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of
performance that can be obtained with different hardware configurations. The MRTA framework decouples response time
analysis from a reliance on context independent WCET values.
Instead, the analysis formulates response times directly from the
demands on different hardware resources.
Original languageEnglish
Title of host publicationRTNS '15
Subtitle of host publicationProceedings of the 23rd International Conference on Real Time and Networks Systems
ISBN (Print)978-1-4503-3591-1
Publication statusPublished - Nov 2015
Event23rd International conference on Real-Time Networks and Systems (RTNS 2015) - , United Kingdom
Duration: 4 Nov 20156 Nov 2015


Conference23rd International conference on Real-Time Networks and Systems (RTNS 2015)
Country/TerritoryUnited Kingdom


  • multiprocessor
  • response time analysis
  • real time systems
  • scheduling
  • processor
  • memory bus

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