Projects per year
Abstract
In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework. This framework is extensible to different multicore architectures, with various types and arrangements of
local memory, and different arbitration policies for the common
interconnects. We instantiate the framework for single level local
data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of
performance that can be obtained with different hardware configurations. The MRTA framework decouples response time
analysis from a reliance on context independent WCET values.
Instead, the analysis formulates response times directly from the
demands on different hardware resources.
local memory, and different arbitration policies for the common
interconnects. We instantiate the framework for single level local
data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of
performance that can be obtained with different hardware configurations. The MRTA framework decouples response time
analysis from a reliance on context independent WCET values.
Instead, the analysis formulates response times directly from the
demands on different hardware resources.
| Original language | English |
|---|---|
| Title of host publication | RTNS '15 |
| Subtitle of host publication | Proceedings of the 23rd International Conference on Real Time and Networks Systems |
| Publisher | ACM |
| Pages | 129-138 |
| ISBN (Print) | 978-1-4503-3591-1 |
| DOIs | |
| Publication status | Published - Nov 2015 |
| Event | 23rd International conference on Real-Time Networks and Systems (RTNS 2015) - , United Kingdom Duration: 4 Nov 2015 → 6 Nov 2015 |
Conference
| Conference | 23rd International conference on Real-Time Networks and Systems (RTNS 2015) |
|---|---|
| Country/Territory | United Kingdom |
| Period | 4/11/15 → 6/11/15 |
Keywords
- multiprocessor
- response time analysis
- real time systems
- scheduling
- processor
- memory bus
Projects
- 2 Finished
-
INRIA International Chair
Davis, R. I. (Principal investigator)
1/10/14 → 30/09/19
Project: Other project › Research collaboration
-
MCC: Mixed Criticality Embedded Systems on Many-Core Platforms
Burns, A. (Principal investigator), Bate, I. J. (Co-investigator), Davis, R. I. (Co-investigator), Soares Indrusiak, L. (Co-investigator) & Harbin, J. R. (Researcher)
1/04/13 → 30/09/16
Project: Research project (funded) › Research