By the same authors

A Generic and Compositional Framework for Multicore Response Time Analysis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Publication details

Title of host publicationRTNS '15
DatePublished - Nov 2015
Pages129-138
PublisherACM
Original languageEnglish
ISBN (Print)978-1-4503-3591-1

Abstract

In this paper, we introduce a Multicore Response Time Analysis (MRTA) framework. This framework is extensible to different multicore architectures, with various types and arrangements of
local memory, and different arbitration policies for the common
interconnects. We instantiate the framework for single level local
data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of
performance that can be obtained with different hardware configurations. The MRTA framework decouples response time
analysis from a reliance on context independent WCET values.
Instead, the analysis formulates response times directly from the
demands on different hardware resources.

    Research areas

  • multiprocessor , response time analysis, real time systems, scheduling, processor, memory bus

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