A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems

TY - JOUR

T1 - A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems

AU - Gomony, Manil Dev

AU - Garside, Jamie

AU - Akesson, Benny

AU - Audsley, Neil

AU - Goossens, Kees

N1 - Copyright © 2016 IEEE. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.

PY - 2017/2/1

Y1 - 2017/2/1

N2 - Embedded systems are increasingly based on multi-core platforms to accommodate a growing number of applications, some of which have real-time requirements. Resources, such as off-chip DRAM, are typically shared between the applications using memory interconnects with different arbitration polices to cater to diverse bandwidth and latency requirements. However, traditional centralized interconnects are not scalable as the number of clients increase. Similarly, current distributed interconnects either cannot satisfy the diverse requirements or have decoupled arbitration stages, resulting in larger area, power and worst-case latency. The four main contributions of this article are: 1) a Globally Arbitrated Memory Tree (GAMT) with a distributed architecture that scales well with the number of cores, 2) an RTL-level implementation that can be configured with five arbitration policies (three distinct and two as special cases), 3) the concept of mixed arbitration policies that allows the policy to be selected individually per core, and 4) a worst-case analysis for a mixed arbitration policy that combines TDM and FBSP arbitration. We compare the performance of GAMT with centralized implementations and show that it can run up to four times faster and have over 51 and 37 percent reduction in area and power consumption, respectively, for a given bandwidth.

AB - Embedded systems are increasingly based on multi-core platforms to accommodate a growing number of applications, some of which have real-time requirements. Resources, such as off-chip DRAM, are typically shared between the applications using memory interconnects with different arbitration polices to cater to diverse bandwidth and latency requirements. However, traditional centralized interconnects are not scalable as the number of clients increase. Similarly, current distributed interconnects either cannot satisfy the diverse requirements or have decoupled arbitration stages, resulting in larger area, power and worst-case latency. The four main contributions of this article are: 1) a Globally Arbitrated Memory Tree (GAMT) with a distributed architecture that scales well with the number of cores, 2) an RTL-level implementation that can be configured with five arbitration policies (three distinct and two as special cases), 3) the concept of mixed arbitration policies that allows the policy to be selected individually per core, and 4) a worst-case analysis for a mixed arbitration policy that combines TDM and FBSP arbitration. We compare the performance of GAMT with centralized implementations and show that it can run up to four times faster and have over 51 and 37 percent reduction in area and power consumption, respectively, for a given bandwidth.

KW - GAMT

KW - globally arbitrated memory tree

KW - latency-rate servers

KW - mixed-time-criticality

KW - Real-time systems

KW - scalability

KW - shared memory

UR - http://www.scopus.com/inward/record.url?scp=85009971930&partnerID=8YFLogxK

U2 - 10.1109/TC.2016.2595581

DO - 10.1109/TC.2016.2595581

M3 - Article

AN - SCOPUS:85009971930

SN - 0018-9340

VL - 66

SP - 212

EP - 225

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 2

M1 - 7523935

ER -