A hardware immune system for benchmark state machine error detection

D Bradley, A Tyrrell

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.

Original languageEnglish
Title of host publicationCEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2
Place of PublicationNEW YORK
PublisherIEEE
Pages813-818
Number of pages6
ISBN (Print)0-7803-7282-4
Publication statusPublished - 2002
EventIEEE World Congress on Computational Intelligence (WCCI2002) - HONOLULU
Duration: 12 May 200217 May 2002

Conference

ConferenceIEEE World Congress on Computational Intelligence (WCCI2002)
CityHONOLULU
Period12/05/0217/05/02

Keywords

  • CIRCUITS
  • DESIGN

Cite this