A hardware immune system for benchmark state machine error detection

D Bradley; A Tyrrell

A hardware immune system for benchmark state machine error detection

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.

Original language	English
Title of host publication	CEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2
Place of Publication	NEW YORK
Publisher	IEEE
Pages	813-818
Number of pages	6
ISBN (Print)	0-7803-7282-4
Publication status	Published - 2002
Event	IEEE World Congress on Computational Intelligence (WCCI2002) - HONOLULU Duration: 12 May 2002 → 17 May 2002

Conference

Conference	IEEE World Congress on Computational Intelligence (WCCI2002)
City	HONOLULU
Period	12/05/02 → 17/05/02

Keywords

CIRCUITS
DESIGN

Cite this

@inproceedings{78e120b870e54c6c86637997cce5b4c3,

title = "A hardware immune system for benchmark state machine error detection",

abstract = "A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.",

keywords = "CIRCUITS, DESIGN",

author = "D Bradley and A Tyrrell",

year = "2002",

language = "English",

isbn = "0-7803-7282-4",

pages = "813--818",

booktitle = "CEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2",

publisher = "IEEE",

address = "United States",

note = "IEEE World Congress on Computational Intelligence (WCCI2002) ; Conference date: 12-05-2002 Through 17-05-2002",

}

TY - GEN

T1 - A hardware immune system for benchmark state machine error detection

AU - Bradley, D

AU - Tyrrell, A

PY - 2002

Y1 - 2002

N2 - A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.

AB - A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.

KW - CIRCUITS

KW - DESIGN

M3 - Conference contribution

SN - 0-7803-7282-4

SP - 813

EP - 818

BT - CEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2

PB - IEEE

CY - NEW YORK

T2 - IEEE World Congress on Computational Intelligence (WCCI2002)

Y2 - 12 May 2002 through 17 May 2002

ER -