Abstract
A novel error detection mechanism is demonstrated for integration into a hardware fault tolerant system. Inspiration is taken from principles of immunology to create a hardware immune system that runs in real-time hardware and continuously monitors a finite state machine architecture for errors. The work is demonstrated through immunisation of the ISCAS'89 benchmark state machine data set.
Original language | English |
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Title of host publication | CEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2 |
Place of Publication | NEW YORK |
Publisher | IEEE |
Pages | 813-818 |
Number of pages | 6 |
ISBN (Print) | 0-7803-7282-4 |
Publication status | Published - 2002 |
Event | IEEE World Congress on Computational Intelligence (WCCI2002) - HONOLULU Duration: 12 May 2002 → 17 May 2002 |
Conference
Conference | IEEE World Congress on Computational Intelligence (WCCI2002) |
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City | HONOLULU |
Period | 12/05/02 → 17/05/02 |
Keywords
- CIRCUITS
- DESIGN