A hardware implementation of an embryonic architecture using Virtex (R) FPGAs

C Ortega; A Tyrrell

A hardware implementation of an embryonic architecture using Virtex (R) FPGAs

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex (R) FPGA from Xilinx (TM), The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a took-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.

Original language	English
Title of host publication	EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS
Editors	J Miller, A Thompson, P Thomson, TC Fogarty
Place of Publication	BERLIN
Publisher	Springer
Pages	155-164
Number of pages	10
ISBN (Print)	3-540-67338-5
Publication status	Published - 2000
Event	3rd International Conference on Evolvable Systems (ICES 2000) - EDINBURGH Duration: 17 Apr 2000 → 19 Apr 2000

Conference

Conference	3rd International Conference on Evolvable Systems (ICES 2000)
City	EDINBURGH
Period	17/04/00 → 19/04/00

Keywords

ARRAYS

Cite this

@inproceedings{7d7431dd000d4d39a7d2788a5e17382c,

title = "A hardware implementation of an embryonic architecture using Virtex (R) FPGAs",

abstract = "This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex (R) FPGA from Xilinx (TM), The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a took-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.",

keywords = "ARRAYS",

author = "C Ortega and A Tyrrell",

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editor = "J Miller and A Thompson and P Thomson and TC Fogarty",

booktitle = "EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS",

publisher = "Springer",

address = "Germany",

note = "3rd International Conference on Evolvable Systems (ICES 2000) ; Conference date: 17-04-2000 Through 19-04-2000",

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T1 - A hardware implementation of an embryonic architecture using Virtex (R) FPGAs

AU - Ortega, C

AU - Tyrrell, A

PY - 2000

Y1 - 2000

N2 - This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex (R) FPGA from Xilinx (TM), The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a took-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.

AB - This paper presents a new version of the MUXTREE embryonic cell suitable for implementation in a commercial Virtex (R) FPGA from Xilinx (TM), The main characteristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a took-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation, the circuit was downloaded to a Virtex FPGA. Results show that not only it is possible to implement many embryonic cells on one device, but also the reconfiguration strategies allow a level of fault tolerance to be achieved.

KW - ARRAYS

M3 - Conference contribution

SN - 3-540-67338-5

SP - 155

EP - 164

BT - EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS

A2 - Miller, J

A2 - Thompson, A

A2 - Thomson, P

A2 - Fogarty, TC

PB - Springer

CY - BERLIN

T2 - 3rd International Conference on Evolvable Systems (ICES 2000)

Y2 - 17 April 2000 through 19 April 2000

ER -