A high abstraction, high accuracy power estimation model for networks-on-chip

TY - CONF

T1 - A high abstraction, high accuracy power estimation model for networks-on-chip

AU - Ost, Luciano

AU - Guindani, Guilherme

AU - Indrusiak, Leandro Soares

AU - Reinbrecht, Cezar

AU - Raupp, Thiago

AU - Moraes, Fernando

PY - 2009

Y1 - 2009

N2 - Due to the vast number of alternatives in the design space of NoC-based MPSoCs, fast and accurate performance evaluation approaches can result in earlier - and often better - design decisions. Important design metrics for mobile embedded systems include power dissipation and energy consumption. To speed-up the evaluation of such metrics, state-of-the-art research proposes abstract models of the NoC interconnect, employing, for example, TLM SystemC, analytical descriptions and graph descriptions. Power parameters used at higher abstraction models (e.g. TLM) frequently rely upon data generated at lower abstraction levels (e.g. RTL). This paper presents an abstract model of a NoC coupled with a power estimation model, aiming to provide accurate estimations early on the design flow. Despite being abstract, this model considers typical NoC communication behavior such as congestion and burst transmissions, leading to accurate results compared to industrial tools. A proof-of-concept implementation using the Ptolemy II framework demonstrates the strength of this approach, showing that it is possible to use abstract models to estimate power and energy without incurring excessive accuracy loss. Other benefits of abstract modeling are increased system observability and simplicity of design space exploration. System observability is demonstrated with a graphic tool enabling the visualization of the power dissipation at runtime.

AB - Due to the vast number of alternatives in the design space of NoC-based MPSoCs, fast and accurate performance evaluation approaches can result in earlier - and often better - design decisions. Important design metrics for mobile embedded systems include power dissipation and energy consumption. To speed-up the evaluation of such metrics, state-of-the-art research proposes abstract models of the NoC interconnect, employing, for example, TLM SystemC, analytical descriptions and graph descriptions. Power parameters used at higher abstraction models (e.g. TLM) frequently rely upon data generated at lower abstraction levels (e.g. RTL). This paper presents an abstract model of a NoC coupled with a power estimation model, aiming to provide accurate estimations early on the design flow. Despite being abstract, this model considers typical NoC communication behavior such as congestion and burst transmissions, leading to accurate results compared to industrial tools. A proof-of-concept implementation using the Ptolemy II framework demonstrates the strength of this approach, showing that it is possible to use abstract models to estimate power and energy without incurring excessive accuracy loss. Other benefits of abstract modeling are increased system observability and simplicity of design space exploration. System observability is demonstrated with a graphic tool enabling the visualization of the power dissipation at runtime.

KW - high abstraction modelling

KW - networks-on-chip

KW - power models

UR - http://www.scopus.com/inward/record.url?scp=70949100994&partnerID=8YFLogxK

U2 - http://doi.acm.org/10.1145/1601896.1601936

DO - http://doi.acm.org/10.1145/1601896.1601936

M3 - Paper

SP - 31:1--31:6

T2 - 22nd Annual Symposium on Integrated Circuits and System Design (SBCCI)

Y2 - 31 August 2009 through 3 September 2009

ER -