By the same authors

A high abstraction, high accuracy power estimation model for networks-on-chip

Research output: Contribution to conferencePaper

Author(s)

Department/unit(s)

Conference

Conference22nd Annual Symposium on Integrated Circuits and System Design (SBCCI)
CountryBrazil
CityNatal
Conference date(s)31/08/093/09/09

Publication details

DatePublished - 2009
Original languageEnglish

Abstract

Due to the vast number of alternatives in the design space of NoC-based MPSoCs, fast and accurate performance evaluation approaches can result in earlier - and often better - design decisions. Important design metrics for mobile embedded systems include power dissipation and energy consumption. To speed-up the evaluation of such metrics, state-of-the-art research proposes abstract models of the NoC interconnect, employing, for example, TLM SystemC, analytical descriptions and graph descriptions. Power parameters used at higher abstraction models (e.g. TLM) frequently rely upon data generated at lower abstraction levels (e.g. RTL). This paper presents an abstract model of a NoC coupled with a power estimation model, aiming to provide accurate estimations early on the design flow. Despite being abstract, this model considers typical NoC communication behavior such as congestion and burst transmissions, leading to accurate results compared to industrial tools. A proof-of-concept implementation using the Ptolemy II framework demonstrates the strength of this approach, showing that it is possible to use abstract models to estimate power and energy without incurring excessive accuracy loss. Other benefits of abstract modeling are increased system observability and simplicity of design space exploration. System observability is demonstrated with a graphic tool enabling the visualization of the power dissipation at runtime.

    Research areas

  • high abstraction modelling, networks-on-chip, power models

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