A mechanism for implementing precise exceptions in pipelined processors

S Alli; C Bailey

A mechanism for implementing precise exceptions in pipelined processors

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An exception is precise if all instructions before the faulting instruction have completed and those instructions following it can be restarted from scratch. If all exceptions in a processor are precise, the processor is said to implement the precise exception model. In a pipelined processor, precise exceptions can be difficult to achieve because an instruction may complete before its predecessors have completed. There exist several techniques for implementing precise exceptions, each varying in terms of performance and hardware cost. This paper introduces a novel solution to the precise exception problem and evaluates its predicted performance with respect to other schemes.

Original language	English
Title of host publication	PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN
Editors	H Selvaraj
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	598-602
Number of pages	5
ISBN (Print)	0-7695-2203-3
Publication status	Published - 2004
Event	DSD 2004 - Rennes, France Duration: 31 Aug 2004 → 3 Sept 2004

Conference

Conference	DSD 2004
Country/Territory	France
City	Rennes
Period	31/08/04 → 3/09/04

Keywords

MICROPROCESSOR

Cite this

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title = "A mechanism for implementing precise exceptions in pipelined processors",

abstract = "An exception is precise if all instructions before the faulting instruction have completed and those instructions following it can be restarted from scratch. If all exceptions in a processor are precise, the processor is said to implement the precise exception model. In a pipelined processor, precise exceptions can be difficult to achieve because an instruction may complete before its predecessors have completed. There exist several techniques for implementing precise exceptions, each varying in terms of performance and hardware cost. This paper introduces a novel solution to the precise exception problem and evaluates its predicted performance with respect to other schemes.",

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AU - Bailey, C

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AB - An exception is precise if all instructions before the faulting instruction have completed and those instructions following it can be restarted from scratch. If all exceptions in a processor are precise, the processor is said to implement the precise exception model. In a pipelined processor, precise exceptions can be difficult to achieve because an instruction may complete before its predecessors have completed. There exist several techniques for implementing precise exceptions, each varying in terms of performance and hardware cost. This paper introduces a novel solution to the precise exception problem and evaluates its predicted performance with respect to other schemes.

KW - MICROPROCESSOR

M3 - Conference contribution

SN - 0-7695-2203-3

SP - 598

EP - 602

BT - PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN

A2 - Selvaraj, H

PB - IEEE Computer Society

CY - LOS ALAMITOS

T2 - DSD 2004

Y2 - 31 August 2004 through 3 September 2004

ER -