A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs

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Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the "Golden 20" MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.
Original languageEnglish
Article numberCDT-2018-5115
Number of pages9
JournalIET Computers and Digital Techniques
Early online date17 Dec 2018
Publication statusE-pub ahead of print - 17 Dec 2018

Bibliographical note

This paper is a postprint of a paper submitted to and accepted for publication in
IET Computers and Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library


  • Multi-objective optimization
  • FPGA implementation
  • routability
  • Timing
  • circuit clustering
  • electronic design automation EDA

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