Abstract
A simple model has been developed to characterize
electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence
of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance
of fast and slow logic devices in such a circuit.
| Original language | English |
|---|---|
| Pages (from-to) | 513-519 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electromagnetic Compatibility |
| Volume | 45 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - Aug 2003 |
Bibliographical note
© 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Keywords
- digital circuits
- immunity
- jitter
- radio frequency interference (RFI)
- statistical distribution
- timing delays
- PREDICTION
- SYSTEMS