A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip

TY - GEN

T1 - A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip

AU - Ost, Luciano

AU - Moraes, Fernando G.

AU - Moller, Leandro

AU - Indrusiak, Leandro Soares

AU - Glesner, Manfred

AU - Maatta, Sanna

AU - Nurmi, Jari

PY - 2008

Y1 - 2008

N2 - This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

AB - This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

KW - Networks-on-Chip

KW - Modeling

KW - Performance Evaluation

UR - http://www.scopus.com/inward/record.url?scp=59249096090&partnerID=8YFLogxK

U2 - 10.1145/1404371.1404420

DO - 10.1145/1404371.1404420

M3 - Conference contribution

SN - 978-1-60558-231-3

SP - 170

EP - 175

BT - Proc 21st Symposium on Integrated Circuits and Systems Design (SBCCI)

PB - ACM

CY - New York

ER -