A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip

Luciano Ost, Fernando G. Moraes, Leandro Moller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Maatta, Jari Nurmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

Original languageEnglish
Title of host publicationProc 21st Symposium on Integrated Circuits and Systems Design (SBCCI)
Place of PublicationNew York
Number of pages6
ISBN (Print)978-1-60558-231-3
Publication statusPublished - 2008


  • Networks-on-Chip
  • Modeling
  • Performance Evaluation

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