A Wormhole NoC Protocol for Mixed Criticality Systems

TY - GEN

T1 - A Wormhole NoC Protocol for Mixed Criticality Systems

AU - Burns, A.

AU - Harbin, J.

AU - Indrusiak, L.S.

PY - 2014/12/1

Y1 - 2014/12/1

N2 - Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.

AB - Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.

KW - multiprocessor interconnection networks

KW - network-on-chip

KW - protocols

KW - WPMC protocol

KW - bus-based architectures

KW - credit-based flow control protocols

KW - cycle accurate simulator

KW - message-set generation

KW - mixed criticality systems

KW - multicore platforms

KW - network-on-chip protocols

KW - scenario-based verification

KW - schedulable resource

KW - scheduling model

KW - temporal behaviour

KW - wormhole NoC protocol

KW - wormhole switching

KW - Interference

KW - Ports (Computers)

KW - Routing

KW - Routing protocols

KW - Switches

KW - System-on-chip

KW - fixed priority

KW - mixed criticality

KW - network on chip

KW - scheduling

KW - wormhole routing

U2 - 10.1109/RTSS.2014.13

DO - 10.1109/RTSS.2014.13

M3 - Conference contribution

SN - 9781479972890

SP - 184

EP - 195

BT - Real-Time Systems Symposium (RTSS), 2014 IEEE

PB - IEEE

ER -