Accurate capture of timing parameters in inductively-coupled on-chip interconnects

T  Murgan; C  Schlachta; M  Petrov; L  Indrusiak; Alberto Garcia Ortiz; M  Glesner; R  Reis

Accurate capture of timing parameters in inductively-coupled on-chip interconnects

T Murgan, C Schlachta, M Petrov, L Indrusiak, Alberto Garcia Ortiz, M Glesner, R Reis

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.

Original language	English
Title of host publication	SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
Place of Publication	NEW YORK
Publisher	ACM
Pages	117-122
Number of pages	6
ISBN (Print)	1-58113-947-0
Publication status	Published - 2004

Keywords

on-chip interconnects
inductive coupling
crosstalk
signal delay
interconnect models
INDUCTANCE

Cite this

@inproceedings{6eb6157e52e442d0bc85749c82d5c701,

title = "Accurate capture of timing parameters in inductively-coupled on-chip interconnects",

abstract = "With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.",

keywords = "on-chip interconnects, inductive coupling, crosstalk, signal delay, interconnect models, INDUCTANCE",

author = "T Murgan and C Schlachta and M Petrov and L Indrusiak and {Garcia Ortiz}, Alberto and M Glesner and R Reis",

year = "2004",

language = "English",

isbn = "1-58113-947-0",

pages = "117--122",

booktitle = "SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS",

publisher = "ACM",

address = "United States",

}

TY - GEN

T1 - Accurate capture of timing parameters in inductively-coupled on-chip interconnects

AU - Murgan, T

AU - Schlachta, C

AU - Petrov, M

AU - Indrusiak, L

AU - Garcia Ortiz, Alberto

AU - Glesner, M

AU - Reis, R

PY - 2004

Y1 - 2004

N2 - With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.

AB - With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.

KW - on-chip interconnects

KW - inductive coupling

KW - crosstalk

KW - signal delay

KW - interconnect models

KW - INDUCTANCE

M3 - Conference contribution

SN - 1-58113-947-0

SP - 117

EP - 122

BT - SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS

PB - ACM

CY - NEW YORK

ER -