Achieving minimal and deterministic interrupt execution in stack-based processor architectures

C Bailey

Achieving minimal and deterministic interrupt execution in stack-based processor architectures

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck - the constant movement of stack content to and from memory (stack-spilling). With 70% to 80% of instructions generating a stack-spill (see introduction), performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple 'stack buffers' may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately this introduces an indeterministic element of system behaviour, especially with respect to interrupts.

In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, "stack buffer windowing" is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes.

Original language	English
Title of host publication	PROCEEDINGS OF THE 26TH EUROMICRO CONFERENCE, VOLS I AND II
Editors	F Vajda
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	368-375
Number of pages	8
ISBN (Print)	0-7695-0781-6
Publication status	Published - 2000
Event	26th Euromicro Conference - MAASTRICHT Duration: 5 Sept 2000 → 7 Sept 2000

Conference

Conference	26th Euromicro Conference
City	MAASTRICHT
Period	5/09/00 → 7/09/00

Cite this

@inproceedings{6f995c5e4e8847e6969536335f6ff7e0,

title = "Achieving minimal and deterministic interrupt execution in stack-based processor architectures",

abstract = "Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck - the constant movement of stack content to and from memory (stack-spilling). With 70% to 80% of instructions generating a stack-spill (see introduction), performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple 'stack buffers' may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately this introduces an indeterministic element of system behaviour, especially with respect to interrupts.In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, {"}stack buffer windowing{"} is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes.",

author = "C Bailey",

year = "2000",

language = "English",

isbn = "0-7695-0781-6",

pages = "368--375",

editor = "F Vajda",

booktitle = "PROCEEDINGS OF THE 26TH EUROMICRO CONFERENCE, VOLS I AND II",

publisher = "IEEE Computer Society",

address = "United States",

note = "26th Euromicro Conference ; Conference date: 05-09-2000 Through 07-09-2000",

}

TY - GEN

T1 - Achieving minimal and deterministic interrupt execution in stack-based processor architectures

AU - Bailey, C

PY - 2000

Y1 - 2000

N2 - Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck - the constant movement of stack content to and from memory (stack-spilling). With 70% to 80% of instructions generating a stack-spill (see introduction), performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple 'stack buffers' may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately this introduces an indeterministic element of system behaviour, especially with respect to interrupts.In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, "stack buffer windowing" is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes.

AB - Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck - the constant movement of stack content to and from memory (stack-spilling). With 70% to 80% of instructions generating a stack-spill (see introduction), performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple 'stack buffers' may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately this introduces an indeterministic element of system behaviour, especially with respect to interrupts.In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, "stack buffer windowing" is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes.

M3 - Conference contribution

SN - 0-7695-0781-6

SP - 368

EP - 375

BT - PROCEEDINGS OF THE 26TH EUROMICRO CONFERENCE, VOLS I AND II

A2 - Vajda, F

PB - IEEE Computer Society

CY - LOS ALAMITOS

T2 - 26th Euromicro Conference

Y2 - 5 September 2000 through 7 September 2000

ER -