Abstract
FPGA implementations of complex image processing
algorithms are often limited in flexibility and by the amount of
available chip resources. This article presents a hardware design
of an adaptive self-reconfigurable video processing platform.
Dynamic self-reconfiguration increases a design’s flexibility and
enables the use of FPGAs with a fraction of resources actually
needed by the algorithm. As a case study two implementation
approaches of a complex frame-grabber with a set of dynamically
reconfigurable kernels are evaluated and further improvements
are outlined.
algorithms are often limited in flexibility and by the amount of
available chip resources. This article presents a hardware design
of an adaptive self-reconfigurable video processing platform.
Dynamic self-reconfiguration increases a design’s flexibility and
enables the use of FPGAs with a fraction of resources actually
needed by the algorithm. As a case study two implementation
approaches of a complex frame-grabber with a set of dynamically
reconfigurable kernels are evaluated and further improvements
are outlined.
| Original language | Undefined/Unknown |
|---|---|
| Title of host publication | Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006 |
| Editors | Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres |
| Publisher | Univ. Montpellier II |
| Pages | 183-188 |
| Number of pages | 6 |
| Publication status | Published - 2006 |