Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry

Jose C. S. Palma; Leandro Soares Indrusiak; Fernando G. Moraes; Alberto Garcia Ortiz; Manfred Glesner; Ricardo A. L. Reis

Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry

Jose C. S. Palma, Leandro Soares Indrusiak, Fernando G. Moraes, Alberto Garcia Ortiz, Manfred Glesner, Ricardo A. L. Reis

Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

Original language	English
Pages (from-to)	603-613
Number of pages	11
Journal	INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
Volume	4148
Publication status	Published - 2006

Cite this

@article{9ca8118427014131bd823e77ea21f59f,

title = "Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry",

abstract = "This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.",

author = "Palma, {Jose C. S.} and Indrusiak, {Leandro Soares} and Moraes, {Fernando G.} and Ortiz, {Alberto Garcia} and Manfred Glesner and Reis, {Ricardo A. L.}",

year = "2006",

language = "English",

volume = "4148",

pages = "603--613",

journal = "INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION",

issn = "0302-9743",

publisher = "Springer",

}

Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry. / Palma, Jose C. S.; Indrusiak, Leandro Soares; Moraes, Fernando G. et al.
In: INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, Vol. 4148, 2006, p. 603-613.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry

AU - Palma, Jose C. S.

AU - Indrusiak, Leandro Soares

AU - Moraes, Fernando G.

AU - Ortiz, Alberto Garcia

AU - Glesner, Manfred

AU - Reis, Ricardo A. L.

PY - 2006

Y1 - 2006

N2 - This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

AB - This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

M3 - Article

SN - 0302-9743

VL - 4148

SP - 603

EP - 613

JO - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

JF - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION

ER -