An Evolutionary Approach to Runtime Variability Mapping and Mitigation on a Multi-Reconfigurable Architecture

TY - GEN

T1 - An Evolutionary Approach to Runtime Variability Mapping and Mitigation on a Multi-Reconfigurable Architecture

AU - Bale, Simon Jonathan

AU - Burmester Campos, Pedro

AU - Trefzer, Martin Albrecht

AU - Walker, James Alfred

AU - Tyrrell, Andrew Martin

PY - 2017/5/15

Y1 - 2017/5/15

N2 - Intrinsic device variability has become a significant problem in deep sub-micron technology nodes. The stochastic variations in device performance, which are a result of structural irregularities at the atomic scale, can impact both the yield and reliability of a circuit design. In this paper we describe a novel multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), which can tackle this problem by allowing post-fabrication reconfiguration of the effective transistor gate widths in a circuit. We demonstrate the advantages of this architecture by creating a frequency variability map of the array using ring oscillators in order to ascertain the location of any frequency outliers. We then show that it is possible, using an evolutionary algorithm, to select alternative transistor configurations which minimise the difference in frequency between one of these outliers and the chips median frequency of operation. Such methods can be used to increase system performance and reliability by presenting an array with more uniform performance characteristics.

AB - Intrinsic device variability has become a significant problem in deep sub-micron technology nodes. The stochastic variations in device performance, which are a result of structural irregularities at the atomic scale, can impact both the yield and reliability of a circuit design. In this paper we describe a novel multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), which can tackle this problem by allowing post-fabrication reconfiguration of the effective transistor gate widths in a circuit. We demonstrate the advantages of this architecture by creating a frequency variability map of the array using ring oscillators in order to ascertain the location of any frequency outliers. We then show that it is possible, using an evolutionary algorithm, to select alternative transistor configurations which minimise the difference in frequency between one of these outliers and the chips median frequency of operation. Such methods can be used to increase system performance and reliability by presenting an array with more uniform performance characteristics.

U2 - 10.23919/DATE.2017.7927240

DO - 10.23919/DATE.2017.7927240

M3 - Conference contribution

SN - 978-3-9815370-9-3

SP - 1570

EP - 1575

BT - Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)

PB - IEEE

T2 - 2017 Design, Automation & Test in Europe Conference & Exhibition

Y2 - 27 March 2017 through 31 March 2017

ER -