An extensible framework for multicore response time analysis

TY - JOUR

T1 - An extensible framework for multicore response time analysis

AU - Davis, Robert Ian

AU - Altmeyer, Sebastian

AU - Soares Indrusiak, Leandro

AU - Maiza, Claire

AU - Nelis, Vincent

AU - Reineke, Jan

N1 - © The Author(s) 2017

PY - 2018/7/1

Y1 - 2018/7/1

N2 - In this paper, we introduce a multicore response time analysis (MRTA)framework, which decouples response time analysis from a reliance on context independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

AB - In this paper, we introduce a multicore response time analysis (MRTA)framework, which decouples response time analysis from a reliance on context independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

KW - real time

KW - SCHEDULABILITY ANALYSIS

KW - multicore

KW - multiprocessor

KW - response time analysis

KW - Multicore scheduling

KW - Verification

KW - Timing analysis

UR - http://www.scopus.com/inward/record.url?scp=85024505011&partnerID=8YFLogxK

U2 - 10.1007/s11241-017-9285-4

DO - 10.1007/s11241-017-9285-4

M3 - Article

SN - 0922-6443

VL - 54

SP - 607

EP - 661

JO - Real-Time Systems

JF - Real-Time Systems

IS - 3

ER -