An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Anju P. Johnson; David M. Halliday; Alan G. Millard; Andy M. Tyrrell; Jon Timmis; Junxiu Liu; Jim Harkin; Liam McDaid; Shvan Karim

doi:10.1109/SSCI.2016.7850175

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Anju P. Johnson, David M. Halliday, Alan G. Millard, Andy M. Tyrrell, Jon Timmis, Junxiu Liu, Jim Harkin, Liam McDaid, Shvan Karim

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.

Original language	English
Title of host publication	2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016
Publisher	IEEE
ISBN (Electronic)	9781509042401
DOIs	https://doi.org/10.1109/SSCI.2016.7850175
Publication status	Published - 9 Feb 2017
Event	2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016 - Athens, Greece Duration: 6 Dec 2016 → 9 Dec 2016

Conference

Conference	2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016
Country/Territory	Greece
City	Athens
Period	6/12/16 → 9/12/16

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10.1109/SSCI.2016.7850175Licence: Other

An FPGA-based Hardware-Efficient Fault-Tolerant Astrocyte-Neuron NetworkAccepted author manuscript, 805 KBLicence: Other

Cite this

@inproceedings{3c0f91f61c774d20a35228f082054b2a,

title = "An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network",

abstract = "The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.",

author = "Johnson, {Anju P.} and Halliday, {David M.} and Millard, {Alan G.} and Tyrrell, {Andy M.} and Jon Timmis and Junxiu Liu and Jim Harkin and Liam McDaid and Shvan Karim",

year = "2017",

month = feb,

day = "9",

doi = "10.1109/SSCI.2016.7850175",

language = "English",

booktitle = "2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016",

publisher = "IEEE",

address = "United States",

note = "2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016 ; Conference date: 06-12-2016 Through 09-12-2016",

}

Johnson, AP , Halliday, DM , Millard, AG , Tyrrell, AM , Timmis, J, Liu, J, Harkin, J, McDaid, L & Karim, S 2017, An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. in 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016., 7850175, IEEE, 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016, Athens, Greece, 6/12/16. https://doi.org/10.1109/SSCI.2016.7850175

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AU - Johnson, Anju P.

AU - Halliday, David M.

AU - Millard, Alan G.

AU - Tyrrell, Andy M.

AU - Timmis, Jon

AU - Liu, Junxiu

AU - Harkin, Jim

AU - McDaid, Liam

AU - Karim, Shvan

PY - 2017/2/9

Y1 - 2017/2/9

N2 - The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.

AB - The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.

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M3 - Conference contribution

AN - SCOPUS:85016077181

BT - 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016

PB - IEEE

T2 - 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016

Y2 - 6 December 2016 through 9 December 2016

ER -

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Abstract

Conference

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Self-repairing hardware paradigms based on astrocyte-neuron models

Cite this

An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Abstract

Conference

Access to Document

Other files and links

Projects

Self-repairing hardware paradigms based on astrocyte-neuron models

Cite this