An FPGA-based MVDR beamformer using dichotomous coordinate descent iterations

Jie Liu; Ben Weaver; Yuriy Zakharov; George White

An FPGA-based MVDR beamformer using dichotomous coordinate descent iterations

Jie Liu, Ben Weaver, Yuriy Zakharov, George White

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28kHz.

Original language	English
Title of host publication	2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14
Place of Publication	NEW YORK
Publisher	IEEE
Pages	2551-2556
Number of pages	6
ISBN (Print)	978-1-4244-0352-3
Publication status	Published - 2007
Event	IEEE International Conference on Communications (ICC 2007) - Glasgow Duration: 24 Jun 2007 → 28 Jun 2007

Conference

Conference	IEEE International Conference on Communications (ICC 2007)
City	Glasgow
Period	24/06/07 → 28/06/07

Keywords

MVDR
FPGA
dichotomous coordinate descent
antenna array
ANTENNA

Cite this

@inproceedings{464ec6a6a6724d34b98c36533ad9bca6,

title = "An FPGA-based MVDR beamformer using dichotomous coordinate descent iterations",

abstract = "The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28kHz.",

keywords = "MVDR, FPGA, dichotomous coordinate descent, antenna array, ANTENNA",

author = "Jie Liu and Ben Weaver and Yuriy Zakharov and George White",

year = "2007",

language = "English",

isbn = "978-1-4244-0352-3",

pages = "2551--2556",

booktitle = "2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14",

publisher = "IEEE",

address = "United States",

note = "IEEE International Conference on Communications (ICC 2007) ; Conference date: 24-06-2007 Through 28-06-2007",

}

TY - GEN

T1 - An FPGA-based MVDR beamformer using dichotomous coordinate descent iterations

AU - Liu, Jie

AU - Weaver, Ben

AU - Zakharov, Yuriy

AU - White, George

PY - 2007

Y1 - 2007

N2 - The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28kHz.

AB - The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28kHz.

KW - MVDR

KW - FPGA

KW - dichotomous coordinate descent

KW - antenna array

KW - ANTENNA

M3 - Conference contribution

SN - 978-1-4244-0352-3

SP - 2551

EP - 2556

BT - 2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14

PB - IEEE

CY - NEW YORK

T2 - IEEE International Conference on Communications (ICC 2007)

Y2 - 24 June 2007 through 28 June 2007

ER -