An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

Anju P. Johnson; Rajat Subhra  Chakraborty; Debdeep Mukhopadhyay

doi:10.1109/TCSII.2016.2566262

An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

Anju P. Johnson, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay

Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

True Random Number Generators (TRNGs) play a very important role in modern cryptographic systems. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. We describe the mathematical model of the TRNG operations, and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bitstreams generated from it passes all tests in the NIST statistical testsuite.

Original language	English
Pages (from-to)	452-456
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	4
DOIs	https://doi.org/10.1109/TCSII.2016.2566262
Publication status	Published - 10 May 2016

Bibliographical note

(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details

Keywords

Digital Clock Manager
Dynamic Partial Reconfiguration
field programmable gate arrays (FPGAs)
True Random Number Generators

Access to Document

10.1109/TCSII.2016.2566262

An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details
Accepted author manuscript, 340 KB

Cite this

@article{fd46dbbc840b44a891180dcbcc310266,

title = "An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA",

abstract = "True Random Number Generators (TRNGs) play a very important role in modern cryptographic systems. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. We describe the mathematical model of the TRNG operations, and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bitstreams generated from it passes all tests in the NIST statistical testsuite.",

keywords = "Digital Clock Manager, Dynamic Partial Reconfiguration, field programmable gate arrays (FPGAs), True Random Number Generators",

author = "Johnson, {Anju P.} and Chakraborty, {Rajat Subhra} and Debdeep Mukhopadhyay",

note = "(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. This is an author-produced version of the published paper. Uploaded in accordance with the publisher{\textquoteright}s self-archiving policy. Further copying may not be permitted; contact the publisher for details",

year = "2016",

month = may,

day = "10",

doi = "10.1109/TCSII.2016.2566262",

language = "English",

volume = "64",

pages = "452--456",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "IEEE",

number = "4",

}

TY - JOUR

T1 - An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

AU - Johnson, Anju P.

AU - Chakraborty, Rajat Subhra

AU - Mukhopadhyay, Debdeep

N1 - (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details

PY - 2016/5/10

Y1 - 2016/5/10

N2 - True Random Number Generators (TRNGs) play a very important role in modern cryptographic systems. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. We describe the mathematical model of the TRNG operations, and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bitstreams generated from it passes all tests in the NIST statistical testsuite.

AB - True Random Number Generators (TRNGs) play a very important role in modern cryptographic systems. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. We describe the mathematical model of the TRNG operations, and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bitstreams generated from it passes all tests in the NIST statistical testsuite.

KW - Digital Clock Manager

KW - Dynamic Partial Reconfiguration

KW - field programmable gate arrays (FPGAs)

KW - True Random Number Generators

U2 - 10.1109/TCSII.2016.2566262

DO - 10.1109/TCSII.2016.2566262

M3 - Article

SN - 1549-7747

VL - 64

SP - 452

EP - 456

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 4

ER -