An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

Anju P. Johnson, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay

Research output: Contribution to journalArticlepeer-review


True Random Number Generators (TRNGs) play a very important role in modern cryptographic systems. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. We describe the mathematical model of the TRNG operations, and experimental results for the circuit implemented on a Xilinx Virtex-V FPGA. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bitstreams generated from it passes all tests in the NIST statistical testsuite.
Original languageEnglish
Pages (from-to)452-456
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number4
Publication statusPublished - 10 May 2016

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  • Digital Clock Manager
  • Dynamic Partial Reconfiguration
  • field programmable gate arrays (FPGAs)
  • True Random Number Generators

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