Abstract
This paper presents an approach supporting designer- driven interactive design space exploration for network-on-chip interconnects. It abstracts the functionality of the interconnect using UML interactions, which are in turn used as reference for the development of an actor-oriented model. Such model can be annotated with timing information, thus allowing the validation of the interconnect performance under a given traffic load. The proposed model allows simpler tuning and modification of the interconnect, improved observability and debugging, while presenting acceptable loss of accuracy with regard to a cycle-accurate RTL model.
| Original language | English |
|---|---|
| Pages | 491 -494 |
| DOIs | |
| Publication status | Published - 1 Apr 2008 |
Keywords
- UML interactions
- actor-oriented simulation
- cycle-accurate RTL model
- debugging
- design space exploration
- network-on-chip interconnects
- observability
- register transfer level
- timing information
- traffic load
- Unified Modeling Language
- integrated circuit interconnections
- logic CAD
- network-on-chip
- program debugging
- timing