Automating Verification of State Machines with Reactive Designs and Isabelle/UTP

Research output: Chapter in Book/Report/Conference proceedingConference contribution


State-machine based notations are ubiquitous in the description of component systems, particularly in the robotic domain. To ensure these systems are safe and predictable, formal verification techniques are important, and can be cost-effective if they are both automated and scalable. In this paper, we present a verification approach for a diagrammatic state machine language that utilises theorem proving and a denotational semantics based on Unifying Theories of Programming (UTP). We provide the necessary theory to underpin state machines (including induction theorems for iterative processes), mechanise an action language for states and transitions, and use these to formalise the semantics. We then describe the verification approach, which supports infinite state systems, and exemplify it with a fully automated deadlock-freedom check. The work has been mechanised in our proof tool, Isabelle/UTP, and so also illustrates the use of UTP to build practical verification tools.
Original languageEnglish
Title of host publication15th International Conference on Formal Aspects of Component Software
EditorsPeter Csaba Ölveczky, Kyungmin Bae
Number of pages18
ISBN (Print)9783030021450
Publication statusPublished - 5 Oct 2018

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume11222 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Bibliographical note

© This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details


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