Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip

TY - GEN

T1 - Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip

AU - Soares Indrusiak, Leandro

AU - Harbin, James Robert

AU - Burns, Alan

PY - 2015/7/8

Y1 - 2015/7/8

N2 - Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first aim is to improve the average latency of low-criticality packets following a mode change by allowing NoC arbiters to service them during cycles in which no high-criticality flows can be transmitted. The second aim is to reduce the worst-case latency of high-criticality packets transmitted by the NoC. The former objective improves the system's responsiveness, while the latter contributes to increased resource efficiency. The achieved improvements are evaluated, respectively, by cycle-accurate simulation and by schedulability analysis, showing full delivery of low-criticality packets following a criticality change, and achieving full schedulability in 8.2\% more flowsets than the state of the art.

AB - Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first aim is to improve the average latency of low-criticality packets following a mode change by allowing NoC arbiters to service them during cycles in which no high-criticality flows can be transmitted. The second aim is to reduce the worst-case latency of high-criticality packets transmitted by the NoC. The former objective improves the system's responsiveness, while the latter contributes to increased resource efficiency. The achieved improvements are evaluated, respectively, by cycle-accurate simulation and by schedulability analysis, showing full delivery of low-criticality packets following a criticality change, and achieving full schedulability in 8.2\% more flowsets than the state of the art.

U2 - 10.1109/ECRTS.2015.12

DO - 10.1109/ECRTS.2015.12

M3 - Conference contribution

SN - 978-1-4673-7570-2

T3 - Proceedings: Euromicro Conference on Real-Time Systems

SP - 47

EP - 56

BT - 27th Euromicro Conference on Real-Time Systems (ECRTS15)

PB - IEEE

ER -