Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Mixed-criticality applications executing over a multiprocessor
platform based on Network-on-Chip (NoC) exchange packets of
different criticality levels through the same communication
infrastructure, and transmission of a packet has potential impact
over the latency of all the others. This paper presents NoC
architectural improvements to output port arbitration and mode
change signalling. The first aim is to improve the average latency of
low-criticality packets following a mode change by allowing NoC
arbiters to service them during cycles in which no high-criticality
flows can be transmitted. The second aim is to reduce the worst-case
latency of high-criticality packets transmitted by the NoC. The
former objective improves the system's responsiveness, while the
latter contributes to increased resource efficiency. The achieved
improvements are evaluated, respectively, by cycle-accurate
simulation and by schedulability analysis, showing full delivery of
low-criticality packets following a criticality change, and
achieving full schedulability in 8.2\% more flowsets than the state
of the art.
Original languageEnglish
Title of host publication27th Euromicro Conference on Real-Time Systems (ECRTS15)
Subtitle of host publicationProceedings
Number of pages10
ISBN (Print)978-1-4673-7570-2
Publication statusPublished - 8 Jul 2015

Publication series

NameProceedings: Euromicro Conference on Real-Time Systems
ISSN (Print)1068-3070

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