AXI-IC^RT: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs

Ian Gray; Zhe Jiang; Kecheng Yang; Nathan Fisher; Neil Cameron Audsley; Zheng Dong

doi:10.1109/TC.2022.3179227

AXI-IC^RT: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs

Ian Gray, Zhe Jiang, Kecheng Yang, Nathan Fisher, Neil Cameron Audsley, Zheng Dong

Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

In modern real-time heterogeneous System-on-Chips (SoCs), ensuring the predictability of interconnects is becoming increasingly important. Most of the existing interconnects are mainly designed to achieve high throughput, with their micro-architectures usually based on FIFO queues. The FIFO-based design prevents transaction prioritization based on importance and leads to occurrences of physical priority inversion. Such problems lead to difficulties in ensuring transaction predictability, especially when the system scales to a large number of elements. In this paper, we introduce AXI-Interconnect^{rt} (AXI-IC^{rt}, for short) -- a real-time AXI interconnect for heterogeneous SoCs, which redefines the micro-architecture of interconnects by enabling random accesses of buffered transactions and organizing transactions through compositional scheduling. This hardware-software co-design approach provides predictable and scalable real-time performance for highly integrated SoCs.

Original language	English
Journal	IEEE Transactions on Computers
DOIs	https://doi.org/10.1109/TC.2022.3179227
Publication status	Published - 31 May 2022

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10.1109/TC.2022.3179227

Cite this

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title = "AXI-IC^RT: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs",

abstract = "In modern real-time heterogeneous System-on-Chips (SoCs), ensuring the predictability of interconnects is becoming increasingly important. Most of the existing interconnects are mainly designed to achieve high throughput, with their micro-architectures usually based on FIFO queues. The FIFO-based design prevents transaction prioritization based on importance and leads to occurrences of physical priority inversion. Such problems lead to difficulties in ensuring transaction predictability, especially when the system scales to a large number of elements. In this paper, we introduce AXI-Interconnect^{rt} (AXI-IC^{rt}, for short) -- a real-time AXI interconnect for heterogeneous SoCs, which redefines the micro-architecture of interconnects by enabling random accesses of buffered transactions and organizing transactions through compositional scheduling. This hardware-software co-design approach provides predictable and scalable real-time performance for highly integrated SoCs.",

author = "Ian Gray and Zhe Jiang and Kecheng Yang and Nathan Fisher and Audsley, {Neil Cameron} and Zheng Dong",

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AU - Gray, Ian

AU - Jiang, Zhe

AU - Yang, Kecheng

AU - Fisher, Nathan

AU - Audsley, Neil Cameron

AU - Dong, Zheng

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