C-NNAP: A dedicated platform for binary neural networks

J V Kennedy; J Austin; R Pack; B Cass

C-NNAP: A dedicated platform for binary neural networks

J V Kennedy, J Austin, R Pack, B Cass

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform.

Original language	English
Title of host publication	FIFTH INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS
Place of Publication	EDISON
Publisher	INST ELECTRICAL ENGINEERS INSPEC INC
Pages	161-166
Number of pages	6
ISBN (Print)	0-85296-690-3
Publication status	Published - 1997
Event	5th International Conference on Artificial Neural Networks - CAMBRIDGE Duration: 7 Jul 1997 → 9 Jul 1997

Conference

Conference	5th International Conference on Artificial Neural Networks
City	CAMBRIDGE
Period	7/07/97 → 9/07/97

Cite this

@inproceedings{b67594f204f5416288b3cd29e7f3897c,

title = "C-NNAP: A dedicated platform for binary neural networks",

abstract = "This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform.",

author = "Kennedy, {J V} and J Austin and R Pack and B Cass",

year = "1997",

language = "English",

isbn = "0-85296-690-3",

pages = "161--166",

booktitle = "FIFTH INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS",

publisher = "INST ELECTRICAL ENGINEERS INSPEC INC",

note = "5th International Conference on Artificial Neural Networks ; Conference date: 07-07-1997 Through 09-07-1997",

}

TY - GEN

T1 - C-NNAP: A dedicated platform for binary neural networks

AU - Kennedy, J V

AU - Austin, J

AU - Pack, R

AU - Cass, B

PY - 1997

Y1 - 1997

N2 - This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform.

AB - This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform.

M3 - Conference contribution

SN - 0-85296-690-3

SP - 161

EP - 166

BT - FIFTH INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS

PB - INST ELECTRICAL ENGINEERS INSPEC INC

CY - EDISON

T2 - 5th International Conference on Artificial Neural Networks

Y2 - 7 July 1997 through 9 July 1997

ER -