C-NNAP - A parallel processing architecture for binary neural networks

J.V. Kennedy; J. Austin; R. Pack; B. Cass

doi:10.1109/ICNN.1995.487564

C-NNAP - A parallel processing architecture for binary neural networks

J.V. Kennedy, J. Austin, R. Pack, B. Cass

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995)
Place of Publication	New York
Publisher	IEEE
Pages	1037-1041
Number of pages	4
Volume	2
ISBN (Print)	0780327691
DOIs	https://doi.org/10.1109/ICNN.1995.487564
Publication status	Published - 1995

Bibliographical note

© 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

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10.1109/ICNN.1995.487564

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http://dx.doi.org/10.1109/ICNN.1995.487564

Cite this

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title = "C-NNAP - A parallel processing architecture for binary neural networks",

abstract = "This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations.",

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language = "English",

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C-NNAP - A parallel processing architecture for binary neural networks. / Kennedy, J.V.; Austin, J.; Pack, R. et al.
Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). Vol. 2 New York: IEEE, 1995. p. 1037-1041.

Research output: Chapter in Book/Report/Conference proceeding › Chapter

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