C-NNAP - A parallel processing architecture for binary neural networks

J.V. Kennedy, J. Austin, R. Pack, B. Cass

Research output: Chapter in Book/Report/Conference proceedingChapter


This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995)
Place of PublicationNew York
Number of pages4
ISBN (Print)0780327691
Publication statusPublished - 1995

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