By the same authors

C-NNAP: A dedicated platform for binary neural networks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Publication details

Title of host publicationFIFTH INTERNATIONAL CONFERENCE ON ARTIFICIAL NEURAL NETWORKS
DatePublished - 1997
Pages161-166
Number of pages6
PublisherINST ELECTRICAL ENGINEERS INSPEC INC
Place of PublicationEDISON
Original languageEnglish
ISBN (Print)0-85296-690-3

Abstract

This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform.

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