Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture

S. Huibin; C. Bailey; G. Farrall; N. Hastie; S. Jenkins

doi:10.1109/SOCC.2005.1554449

Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture

S. Huibin, C. Bailey, G. Farrall, N. Hastie, S. Jenkins

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.

Original language	English
Title of host publication	Proceedings of IEEE International System-On-Chip Conference 2005
Pages	33 - 36
DOIs	https://doi.org/10.1109/SOCC.2005.1554449
Publication status	Published - 2005
Event	SOC Conference, 2005 - Washington, DC Duration: 19 Sept 2005 → 23 Sept 2005

Conference

Conference	SOC Conference, 2005
City	Washington, DC
Period	19/09/05 → 23/09/05

Access to Document

10.1109/SOCC.2005.1554449

http://dx.doi.org/10.1109/SOCC.2005.1554449

Cite this

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title = "Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture",

abstract = "This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore{\texttrademark} 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.",

author = "S. Huibin and C. Bailey and G. Farrall and N. Hastie and S. Jenkins",

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doi = "10.1109/SOCC.2005.1554449",

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booktitle = "Proceedings of IEEE International System-On-Chip Conference 2005",

note = "SOC Conference, 2005 ; Conference date: 19-09-2005 Through 23-09-2005",

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AU - Jenkins, S.

PY - 2005

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AB - This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.

U2 - 10.1109/SOCC.2005.1554449

DO - 10.1109/SOCC.2005.1554449

M3 - Conference contribution

SN - 0-7803-9264-7

SP - 33

EP - 36

BT - Proceedings of IEEE International System-On-Chip Conference 2005

T2 - SOC Conference, 2005

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