Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture

S. Huibin, C. Bailey, G. Farrall, N. Hastie, S. Jenkins

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.
Original languageEnglish
Title of host publicationProceedings of IEEE International System-On-Chip Conference 2005
Pages33 - 36
Publication statusPublished - 2005
EventSOC Conference, 2005 - Washington, DC
Duration: 19 Sept 200523 Sept 2005


ConferenceSOC Conference, 2005
CityWashington, DC

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