Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

TY - JOUR

T1 - Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

AU - Harbin, James

AU - Soares Indrusiak, Leandro

N1 - © 2016, Elsevier. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details

PY - 2016/2/1

Y1 - 2016/2/1

N2 - The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simulation models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.

AB - The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simulation models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.

KW - Dynamic power consumption

KW - Network on chip

KW - NoC modelling

KW - Simulation models

KW - TLM

KW - Transaction level modelling

UR - http://www.scopus.com/inward/record.url?scp=84958214050&partnerID=8YFLogxK

U2 - 10.1016/j.sysarc.2016.01.002

DO - 10.1016/j.sysarc.2016.01.002

M3 - Article

AN - SCOPUS:84958214050

SN - 1383-7621

VL - 63

SP - 33

EP - 47

JO - Journal of systems architecture

JF - Journal of systems architecture

ER -