Compiler-directed dynamic memory disambiguation for loop structures

S Alli; C Bailey

doi:10.1109/DSD.2004.1333268

Compiler-directed dynamic memory disambiguation for loop structures

S Alli, C Bailey

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory. This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single parted. Thus, there may be several memory operations outstanding concurrently. Processors alleviate the effects of this restriction by issuing loads ahead of stores. However, the memory references must first be disambiguated in order to ensure correct execution of the program. This paper introduces a technique for disambiguating memory references dynamically. This technique enables the compiler to convey information about the program that is available at compile time but cannot be exploited fully due to practical limitations. The processor can then use this information to issue loads ahead of stores.

Original language	English
Title of host publication	PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN
Editors	H Selvaraj
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	130-134
Number of pages	5
ISBN (Print)	0-7695-2203-3
DOIs	https://doi.org/10.1109/DSD.2004.1333268
Publication status	Published - 2004
Event	DSD 2004 - Rennes, France Duration: 31 Aug 2004 → 3 Sept 2004

Conference

Conference	DSD 2004
Country/Territory	France
City	Rennes
Period	31/08/04 → 3/09/04

Access to Document

10.1109/DSD.2004.1333268

http://dx.doi.org/10.1109/DSD.2004.1333268

Cite this

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title = "Compiler-directed dynamic memory disambiguation for loop structures",

abstract = "The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory. This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single parted. Thus, there may be several memory operations outstanding concurrently. Processors alleviate the effects of this restriction by issuing loads ahead of stores. However, the memory references must first be disambiguated in order to ensure correct execution of the program. This paper introduces a technique for disambiguating memory references dynamically. This technique enables the compiler to convey information about the program that is available at compile time but cannot be exploited fully due to practical limitations. The processor can then use this information to issue loads ahead of stores.",

author = "S Alli and C Bailey",

year = "2004",

doi = "10.1109/DSD.2004.1333268",

language = "English",

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editor = "H Selvaraj",

booktitle = "PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN",

publisher = "IEEE Computer Society",

address = "United States",

note = "DSD 2004 ; Conference date: 31-08-2004 Through 03-09-2004",

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T1 - Compiler-directed dynamic memory disambiguation for loop structures

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AU - Bailey, C

PY - 2004

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AB - The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory. This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single parted. Thus, there may be several memory operations outstanding concurrently. Processors alleviate the effects of this restriction by issuing loads ahead of stores. However, the memory references must first be disambiguated in order to ensure correct execution of the program. This paper introduces a technique for disambiguating memory references dynamically. This technique enables the compiler to convey information about the program that is available at compile time but cannot be exploited fully due to practical limitations. The processor can then use this information to issue loads ahead of stores.

U2 - 10.1109/DSD.2004.1333268

DO - 10.1109/DSD.2004.1333268

M3 - Conference contribution

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EP - 134

BT - PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN

A2 - Selvaraj, H

PB - IEEE Computer Society

CY - LOS ALAMITOS

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