Compiler-directed dynamic memory disambiguation for loop structures

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Publication details

Title of host publicationPROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN
DatePublished - 2004
Pages130-134
Number of pages5
PublisherIEEE COMPUTER SOC
Place of PublicationLOS ALAMITOS
EditorsH Selvaraj
Original languageEnglish
ISBN (Print)0-7695-2203-3

Abstract

The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory. This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single parted. Thus, there may be several memory operations outstanding concurrently. Processors alleviate the effects of this restriction by issuing loads ahead of stores. However, the memory references must first be disambiguated in order to ensure correct execution of the program. This paper introduces a technique for disambiguating memory references dynamically. This technique enables the compiler to convey information about the program that is available at compile time but cannot be exploited fully due to practical limitations. The processor can then use this information to issue loads ahead of stores.

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