Abstract
This paper will address the design of lattice coding systems with the potential for both significant coding gain and very high speed operation, without impractical complexity. The paper discusses the choice of lattice, considering both the performance and the complexity of implementation, and describes two families of lattice which are suitable for hardware implementation. A suitable decoding algorithm is described together with the resulting architecture, and some conclusions are given.
| Original language | English |
|---|---|
| Pages (from-to) | 256-261 |
| Number of pages | 6 |
| Journal | IEE Conference Publication |
| Publication status | Published - 1991 |
| Event | 6th International Conference on Digital Processing of Signals in Communications - Loughborough, Engl Duration: 2 Sept 1991 → 6 Sept 1991 |