By the same authors

Designing function configuration decoders for the PAnDA architecture using multi-objective Cartesian Genetic Programming

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Title of host publicationEvolvable Systems (ICES), 2013 IEEE International Conference on
DatePublished - 1 Apr 2013
Pages96-103
PublisherIEEE
Original languageEnglish

    Research areas

  • circuit optimisation, genetic algorithms, logic design, network topology, performance evaluation, programmable logic arrays, reconfigurable architectures, CAB, FCD designs, MO-CGP, PAnDA architecture, PAnDA prototype chip, area consumption reduction, bio-inspired techniques, circuit topologies, configurable analogue blocks, configuration memory, digital systems, extra configuration memory overhead reduction, function configuration decoder design, logic functionality configuration, multiobjective Cartesian genetic programming, multiobjective strategy, post-fabrication correction, programmable analogue and digital array, rapid prototyping, reconfigurable architecture, variability aware design, Decoding, Field programmable gate arrays, Logic gates, Optimization, Sociology, Statistics, Transistors

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