Projects per year
This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.
|Title of host publication||PRIME: PROCEEDINGS OF THE CONFERENCE 2009 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS|
|Place of Publication||NEW YORK|
|Number of pages||4|
|Publication status||Published - 2009|
- 1 Finished
NanoCMOS: Meeting the Design Challenges of ....
Tyrrell, A., Walker, J. A. & Hilder, J. A.
1/10/06 → 30/09/10
Project: Research project (funded) › Research