Designing Variability Tolerant Logic using Evolutionary Algorithms

TY - GEN

T1 - Designing Variability Tolerant Logic using Evolutionary Algorithms

AU - Hilder, James A.

AU - Walker, James Alfred

AU - Tyrrell, Andy M.

PY - 2009

Y1 - 2009

N2 - This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.

AB - This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.

UR - http://www.scopus.com/inward/record.url?scp=70449514740&partnerID=8YFLogxK

M3 - Conference contribution

SN - 978-1-4244-3732-0

SP - 184

EP - 187

BT - PRIME: PROCEEDINGS OF THE CONFERENCE 2009 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS

PB - IEEE

CY - NEW YORK

ER -