Designing Variability Tolerant Logic using Evolutionary Algorithms

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Title of host publicationPRIME: PROCEEDINGS OF THE CONFERENCE 2009 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS
DatePublished - 2009
Pages184-187
Number of pages4
PublisherIEEE
Place of PublicationNEW YORK
Original languageEnglish
ISBN (Print)978-1-4244-3732-0

Abstract

This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.

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