Digital circuit design using intrinsic evolvable hardware

Y Zhang; S L Smith; A M Tyrrell

Digital circuit design using intrinsic evolvable hardware

Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes the application of intrinsic evolvable hardware to combinational circuit design and synthesis, as an alternative to conventional approaches. This novel reconfigurable architecture is inspired by Cartesian Genetic Programming and dedicated for implementing high performance digital image filters on a custom Xilinx Virtex FPGA xcv1000, together with a flexible local interconnection hierarchy. As a highly parallel architecture, it scales linearly with the filter complexity. It is reconfigured by an external genetic reconfiguration processing unit with a hardware GA implementation embedded. Due to pipelining, parallelization and no function call overhead, it yields a significant speedup of one to two orders of magnitude over a software implementation, which is especially useful for the real-time applications. The experimental results conclude that in terms of computational effort, filtered image signal and implementation cost, the intrinsic evolvable hardware solution outperforms traditional approaches.

Original language	English
Title of host publication	2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS
Editors	RS Zebulum, D Gwaltney, G Hornby, D Keymeulen, F Lohn, A Stoica
Place of Publication	LOS ALAMITOS
Publisher	IEEE Computer Society
Pages	55-62
Number of pages	8
ISBN (Print)	0-7695-2145-2
Publication status	Published - 2004
Event	6th Annual Genetic and Evolutionary Computation Conference (GECCO 2004) - Seattle Duration: 26 Jun 2004 → 30 Jun 2004

Conference

Conference	6th Annual Genetic and Evolutionary Computation Conference (GECCO 2004)
City	Seattle
Period	26/06/04 → 30/06/04

Cite this

@inproceedings{a2fbe9acf677454b8bd3522e099a4964,

title = "Digital circuit design using intrinsic evolvable hardware",

abstract = "This paper describes the application of intrinsic evolvable hardware to combinational circuit design and synthesis, as an alternative to conventional approaches. This novel reconfigurable architecture is inspired by Cartesian Genetic Programming and dedicated for implementing high performance digital image filters on a custom Xilinx Virtex FPGA xcv1000, together with a flexible local interconnection hierarchy. As a highly parallel architecture, it scales linearly with the filter complexity. It is reconfigured by an external genetic reconfiguration processing unit with a hardware GA implementation embedded. Due to pipelining, parallelization and no function call overhead, it yields a significant speedup of one to two orders of magnitude over a software implementation, which is especially useful for the real-time applications. The experimental results conclude that in terms of computational effort, filtered image signal and implementation cost, the intrinsic evolvable hardware solution outperforms traditional approaches.",

author = "Y Zhang and Smith, {S L} and Tyrrell, {A M}",

year = "2004",

language = "English",

isbn = "0-7695-2145-2",

pages = "55--62",

editor = "RS Zebulum and D Gwaltney and G Hornby and D Keymeulen and F Lohn and A Stoica",

booktitle = "2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS",

publisher = "IEEE Computer Society",

address = "United States",

note = "6th Annual Genetic and Evolutionary Computation Conference (GECCO 2004) ; Conference date: 26-06-2004 Through 30-06-2004",

}

Zhang, Y, Smith, SL & Tyrrell, AM 2004, Digital circuit design using intrinsic evolvable hardware. in RS Zebulum, D Gwaltney, G Hornby, D Keymeulen, F Lohn & A Stoica (eds), 2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS. IEEE Computer Society, LOS ALAMITOS, pp. 55-62, 6th Annual Genetic and Evolutionary Computation Conference (GECCO 2004), Seattle, 26/06/04.

Digital circuit design using intrinsic evolvable hardware. / Zhang, Y; Smith, S L ; Tyrrell, A M.
2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS. ed. / RS Zebulum; D Gwaltney; G Hornby; D Keymeulen; F Lohn; A Stoica. LOS ALAMITOS: IEEE Computer Society, 2004. p. 55-62.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper describes the application of intrinsic evolvable hardware to combinational circuit design and synthesis, as an alternative to conventional approaches. This novel reconfigurable architecture is inspired by Cartesian Genetic Programming and dedicated for implementing high performance digital image filters on a custom Xilinx Virtex FPGA xcv1000, together with a flexible local interconnection hierarchy. As a highly parallel architecture, it scales linearly with the filter complexity. It is reconfigured by an external genetic reconfiguration processing unit with a hardware GA implementation embedded. Due to pipelining, parallelization and no function call overhead, it yields a significant speedup of one to two orders of magnitude over a software implementation, which is especially useful for the real-time applications. The experimental results conclude that in terms of computational effort, filtered image signal and implementation cost, the intrinsic evolvable hardware solution outperforms traditional approaches.

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BT - 2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS

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A2 - Gwaltney, D

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A2 - Stoica, A

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