TY - JOUR
T1 - Engineering a DSL for Software Traceability
AU - Drivalos, Nikolaos
AU - Kolovos, Dimitrios S.
AU - Paige, Richard F.
AU - Fernandes, Kiran J.
PY - 2009
Y1 - 2009
N2 - The software artefacts at different levels of abstraction and at different stages of the development process are closely inter-related. For developers to stay in control of the development process, traceability information must be maintained. In this paper, we present the engineering of the Traceability Metamodelling Language (TML), a metamodelling language dedicated to defining traceability metamodels. We present the abstract syntax of the language and its semantics, which are defined using a translational approach. Finally, we provide a case study that demonstrates the construction of a traceability metamodel that captures traceability information between two metamodels using TML.
AB - The software artefacts at different levels of abstraction and at different stages of the development process are closely inter-related. For developers to stay in control of the development process, traceability information must be maintained. In this paper, we present the engineering of the Traceability Metamodelling Language (TML), a metamodelling language dedicated to defining traceability metamodels. We present the abstract syntax of the language and its semantics, which are defined using a translational approach. Finally, we provide a case study that demonstrates the construction of a traceability metamodel that captures traceability information between two metamodels using TML.
UR - http://www.scopus.com/inward/record.url?scp=67649962152&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-00434-6_10
DO - 10.1007/978-3-642-00434-6_10
M3 - Article
SN - 0302-9743
VL - 5452
SP - 151
EP - 167
JO - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
JF - INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
ER -