TY - CONF
T1 - Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms
T2 - A layered approach
AU - Indrusiak, L.S.
AU - Ost, L.C.
AU - Moraes, F.G.
AU - Maatta, S.
AU - Nurmi, J.
AU - Moller, L.
AU - Glesner, M.
PY - 2010/7/1
Y1 - 2010/7/1
N2 - The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.
AB - The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.
KW - ESL design
KW - NoC-based multiprocessor platform model
KW - application functionality
KW - communication latency
KW - on-chip multiprocessing platforms
KW - simulation analysis
KW - static analysis
KW - integrated circuit design
KW - multiprocessing systems
KW - network-on-chip
UR - http://www.scopus.com/inward/record.url?scp=77956600909&partnerID=8YFLogxK
U2 - 10.1109/INDIN.2010.5549443
DO - 10.1109/INDIN.2010.5549443
M3 - Paper
SP - 148
EP - 153
ER -