Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

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Publication details

DatePublished - 1 Jul 2010
Original languageEnglish


The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

    Research areas

  • ESL design, NoC-based multiprocessor platform model, application functionality, communication latency, on-chip multiprocessing platforms, simulation analysis, static analysis, integrated circuit design, multiprocessing systems, network-on-chip

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