Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Research output: Contribution to conferencePaper

Standard

Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms : A layered approach. / Indrusiak, L.S.; Ost, L.C.; Moraes, F.G.; Maatta, S.; Nurmi, J.; Moller, L.; Glesner, M.

2010. 148 -153.

Research output: Contribution to conferencePaper

Harvard

Indrusiak, LS, Ost, LC, Moraes, FG, Maatta, S, Nurmi, J, Moller, L & Glesner, M 2010, 'Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach' pp. 148 -153. https://doi.org/10.1109/INDIN.2010.5549443

APA

Indrusiak, L. S., Ost, L. C., Moraes, F. G., Maatta, S., Nurmi, J., Moller, L., & Glesner, M. (2010). Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach. 148 -153. https://doi.org/10.1109/INDIN.2010.5549443

Vancouver

Indrusiak LS, Ost LC, Moraes FG, Maatta S, Nurmi J, Moller L et al. Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach. 2010. https://doi.org/10.1109/INDIN.2010.5549443

Author

Indrusiak, L.S. ; Ost, L.C. ; Moraes, F.G. ; Maatta, S. ; Nurmi, J. ; Moller, L. ; Glesner, M. / Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms : A layered approach.

Bibtex - Download

@conference{8e54ad21ac6748eeb034648af540be2b,
title = "Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach",
abstract = "The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.",
keywords = "ESL design, NoC-based multiprocessor platform model, application functionality, communication latency, on-chip multiprocessing platforms, simulation analysis, static analysis, integrated circuit design, multiprocessing systems, network-on-chip",
author = "L.S. Indrusiak and L.C. Ost and F.G. Moraes and S. Maatta and J. Nurmi and L. Moller and M. Glesner",
year = "2010",
month = "7",
day = "1",
doi = "10.1109/INDIN.2010.5549443",
language = "English",
pages = "148 --153",

}

RIS (suitable for import to EndNote) - Download

TY - CONF

T1 - Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms

T2 - A layered approach

AU - Indrusiak, L.S.

AU - Ost, L.C.

AU - Moraes, F.G.

AU - Maatta, S.

AU - Nurmi, J.

AU - Moller, L.

AU - Glesner, M.

PY - 2010/7/1

Y1 - 2010/7/1

N2 - The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

AB - The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

KW - ESL design

KW - NoC-based multiprocessor platform model

KW - application functionality

KW - communication latency

KW - on-chip multiprocessing platforms

KW - simulation analysis

KW - static analysis

KW - integrated circuit design

KW - multiprocessing systems

KW - network-on-chip

UR - http://www.scopus.com/inward/record.url?scp=77956600909&partnerID=8YFLogxK

U2 - 10.1109/INDIN.2010.5549443

DO - 10.1109/INDIN.2010.5549443

M3 - Paper

SP - 148

EP - 153

ER -