Evolving Variability-Tolerant CMOS Designs

TY - JOUR

T1 - Evolving Variability-Tolerant CMOS Designs

AU - Walker, James Alfred

AU - Hilder, James A.

AU - Tyrrell, Andy M.

PY - 2008/9

Y1 - 2008/9

N2 - As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerant CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully evolve unconventional designs for logic gates, whilst an inverter design also shows signs of variability-tolerance.

AB - As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerant CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully evolve unconventional designs for logic gates, whilst an inverter design also shows signs of variability-tolerance.

KW - SIMULATION

KW - DEVICES

UR - http://www.scopus.com/inward/record.url?scp=70349849800&partnerID=8YFLogxK

M3 - Article

VL - 5216

SP - 308

EP - 319

JO - 8th International Conference on Evolvable Systems

JF - 8th International Conference on Evolvable Systems

ER -