Evolving Variability-Tolerant CMOS Designs

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As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional designs. In this paper, two approaches are proposed for evolving unconventional variability-tolerant CMOS designs: one uses a simple Genetic Algorithm, whilst the other uses Cartesian Genetic Programming. Both approaches successfully evolve unconventional designs for logic gates, whilst an inverter design also shows signs of variability-tolerance.

Original languageEnglish
Pages (from-to)308-319
Number of pages12
Journal8th International Conference on Evolvable Systems
Publication statusPublished - Sept 2008



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