Exploring NoC-Based MPSoC Design Space with Power Estimation Models

Luciano Ost; Guilherme Montez Guindani; Fernando Gehm Moraes; Leandro Soares Indrusiak; Sanna Maatta

doi:10.1109/MDT.2010.116

Exploring NoC-Based MPSoC Design Space with Power Estimation Models

Luciano Ost, Guilherme Montez Guindani, Fernando Gehm Moraes, Leandro Soares Indrusiak, Sanna Maatta

Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.

Original language	English
Article number	5601672
Pages (from-to)	16-29
Number of pages	14
Journal	IEEE Design and Test of Computers
Volume	28
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2010.116
Publication status	Published - Mar 2011

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http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5601672

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Exploring NoC-Based MPSoC Design Space with Power Estimation Models

Abstract

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